The present invention relates to a semiconductor device having a test element group (TEG) pattern, a method of manufacturing the semiconductor device, and a method of designing the semiconductor device.
The semiconductor device is provided with a TEG pattern for evaluating the displacement of a pattern. For example, Japanese Unexamined Patent Application Publication NO. Sho 62(1987)-86741 discloses that an electrically conductive state between a first thin film electrode array arranged at first pitches and a second thin film electrode array arranged at second pitches is confirmed to evaluate a positional displacement therebetween.
Also, Japanese Unexamined Patent Application Publication NO. 2008-270277 discloses a positional displacement detection pattern that can detect a relative positional displacement between wirings and via plugs.
Japanese Unexamined Patent Application Publication NO. 2000-164497 discloses that an alignment mark is formed by a part of a trench separation film, and a gate electrode film over the alignment mark is removed.